The present invention relates to a memory apparatus including a semiconductor memory constructed such that memory data are batch-erased in a block unit.
Recently, a flash memory (flash EEPROM) has been noticed as a semiconductor memory for replacement of with a magnetic memory such as a hard disk, a floppy disk, etc. The flash memory is a nonvolatile semiconductor memory in which power consumption is small and data can be electrically rewritten. Further, the flash memory is light in weight and is compact and has a preferable earthquake proof property. Accordingly, usage of the flash memory to a portable device, etc. is enlarged.
For example, a memory array within a chip of the flash memory is divided into plural memory blocks such as 512 memory blocks. Each block is divided into plural pages such as 16 pages or sectors. Normally, programming (write-in) and reading-out are performed in a page unit and an erasing operation is performed in a block unit.
In general, a dedicated controller for only the flash memory is used in a computer system using the flash memory in an external memory unit. A host computer (e.g., a personal computer) gives writing and reading commands to this controller. The controller directly controls writing and reading operations of data with respect to the flash memory by receiving the commands from the host computer. Further, the controller performs a memory managing operation such as data rewriting every block and the batch erasure, etc.
When such a memory administration operation is performed, the controller must be able to know blocks (in use) including memory data and blocks (empty blocks in an empty state) including no memory data within each flash memory at any time. Therefore, an address conversion table for registering blocks used at present and an empty block table for registering empty blocks in an empty state at present are formed within a RAM (generally SRAM) separately arranged from the flash memory. The controller refers to or searches for these tables every time writing commands are transmitted from the host computer.
When a memory region within the flash memory is divided into 512 blocks as mentioned above in the empty block table in the conventional flash memory system, 512 address data storing positions (address data storing positions) are formed in this empty block table. Address data of 9 bits for designating a memory position (physical address) of one empty block in an empty state within this flash memory is stored every address data storing position.
An empty block registered in this table to be used most early is designated by a read pointer. The controller refers to the read pointer when an empty block is required to write new data, etc. Thus, since the read pointer designates an address data storing position, the controller reads address data stored to this address data storing position and gets access to the empty block by this read address data.
When the address data is thus read out of the address data storing position, the read pointer increments a pointer value by one and designates the next address data storing position. Data (address data) in address data storing positions undesignated by the read pointer may be erased immediately after the address data have been read. Otherwise, these data (address data) may be held until the next new data (address data) are stored (registered).
The controller refers to a write pointer when the used block is changed to an empty block in an empty state by the batch erasure. Thereafter, the write pointer increments a pointer value by one and designates the next address data storing position.
The conventional empty block table mentioned above requires a memory capacity (512.times.9 bits) obtained by multiplying the total number (512 in the above example) of address data storing positions K by a bit number (9 bits in the above example) of block address data with respect to one flash memory. The number of address data storing positions equal to the total block number (512) is set within this table since all the blocks can simultaneously attain empty states in a certain case.
In the actual flash memory system, many (e.g., 10) flash memories are connected to the same bus and one controller generally controls operations of these flash memories. The number of empty block tables corresponding to the total number of flash memories is set within a table memory (SRAM).
In the conventional system, the memory capacity (512.times.9 bits per one table) of the above-mentioned empty block tables is large so that a large-scale expensive table memory (SRAM) is required. Accordingly, it is difficult to construct the controller and the table memory (SRAM) by one chip, which becomes one factor limiting a table managing function and system performance.